RE: [sv-bc] RE: Agenda: May 10 SV-BC Meeting

I've another issue with virtual interfaces usage please see below:
In attached code signal sig_read is driven by both procedural assign via
virtual interface and continous assign via port connection
Should it be error in simulator (variables cannot be driven by mixture of
procedural and continuous assignmenr)?
if not then How should be the value of sig_read in such case resolved?
In below code value sig_read should be always == z or it should be == 1 at
the eof???
Is this issue known? Does improvements described in "Is There a Future for
SystemVerilog Interfaces" resolve this issue?
 
 
interface iface;
 logic sig_read;
endinterface
 
module dut(output reg read);
initial read = 1'bz;
initial #1 read <= 1'bz;
endmodule
 
class C;
 virtual iface vi;
 function drive;
  vi.sig_read<=1; //<<<<<procedural drive to top.iface_i.sig_read
 endfunction
endclass
 
module top;
 iface iface_i();
 dut uut(iface_i.sig_read); //continous assign to top.iface_i.sig_read
 C c =new();
 initial begin
 $monitor(iface_i.sig_read, uut.read);
  c.vi=iface_i;
  #1 c.drive();
  #1;
 end
endmodule
 

 
DANiel

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Bresticker, Shalom
Sent: Sunday, May 09, 2010 9:29 PM
To: Bresticker, Shalom; Maidment, Matthew R; sv-bc@eda.org
Subject: [sv-bc] RE: Agenda: May 10 SV-BC Meeting

Gord approved to send the paper, attached.

Shalom

> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
> Bresticker, Shalom
> Sent: Sunday, May 09, 2010 9:56 AM
> To: Maidment, Matthew R; sv-bc@eda.org
> Subject: [sv-bc] RE: Agenda: May 10 SV-BC Meeting
>
> The DVCON 2009 interface paper was called, "Is There a Future for
> SystemVerilog Interfaces?"
>
> Abstract:
> The SystemVerilog interface is intended to be a powerful modeling
> construct for describing hardware interconnect in a very general
> manner that is applicable to both testbench and synthesizable RTL
> design applications. In this paper we argue that the SystemVerilog
> interface construct is inadequately specified, insufficiently powerful
> for real applications, and impossible to implement consistently in its
> current form. We then review the application areas that interfaces
> were intended to address, and propose some possible solutions for
> these shortcomings.
>
> It can be requested at
> http://www.mentor.com/products/fv/techpubs/is-there-a-future-f
> or-systemverilog-interfaces--49113 or
> http://www.techonline.com/learning/techpaper/217701248
>
> If Mentor has no objections, I can post it directly to the reflector.
>
> Shalom
>
>
> > Outstanding
> 04/26/10 Gord or anyone else provide URL or copy of interface paper
> if
> publicly available.
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