[sv-bc] Macro call split across multiple files

Hi,

Should a macro call be allowed to split across multiple files ?
For example,

File a.v
---------
`define MAC(x) wire x

module top;
   `MAC(

File b.v
--------
w);
endmodule

When the input order is "a.v b.v", I can find some standard tools pass
it while some other
errors out while parsing.

I do not find LRM to explicitly allow/restrict it anywhere.

Thanks,
Sourasis

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