Re: [sv-bc] Type of a concat expression

From: Surya Pratik Saha <spsaha@cal.interrasystems.com>
Date: Mon Jun 14 2010 - 06:09:09 PDT

Also, it is not clear what is the state (4 state or 2 state) of concatenation or any other expression. Is {1,bx, 1,b0} is equivalent to 'logic [1:0]'? I think we need to make lots of assumptions to determine the type of expression unlike VHDL.

Regards
Surya

-------- Original Message  --------
Subject: Re:[sv-bc] Type of a concat expression
From: Surya Pratik Saha <spsaha@cal.interrasystems.com>
To: Bresticker, Shalom <shalom.bresticker@intel.com>
Cc: "sv-bc@eda.org" <sv-bc@eda.org>, "'Pradip Mukhopadhyay'" <pradip@cal.interrasystems.com>, Subhankar Ghosh <sghosh@cal.interrasystems.com>
Date: Monday, June 14, 2010 5:53:39 PM

Hi Shalom,
Thanks for your response. But I think we should have a list of all self determined result type of an expression. For e.g. what is the type of a binary expression?

Regards
Surya
  

-------- Original Message  --------
Subject: Re:[sv-bc] Type of a concat expression
From: Bresticker, Shalom <shalom.bresticker@intel.com>
To: Surya Pratik Saha <spsaha@cal.interrasystems.com>, sv-bc@eda.org <sv-bc@eda.org>
Cc: "'Pradip Mukhopadhyay'" <pradip@cal.interrasystems.com>, Subhankar Ghosh <sghosh@cal.interrasystems.com>
Date: Monday, June 14, 2010 5:44:29 PM

The LRM says (11.4.12)

 

"The concatenation is treated as a packed vector of bits...One or more bits of a concatenation can be selected as if the concatenation were a packed array with the range [n-1:0]."

 

and (11.8.1)

"— Concatenate results are unsigned, regardless of the operands."

Note that 'byte' is signed.

Shalom

 

---

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Surya Pratik Saha
Sent: Monday, June 14, 2010 3:04 PM
To: sv-bc@eda.org
Cc: 'Pradip Mukhopadhyay'; Subhankar Ghosh
Subject: [sv-bc] Type of a concat expression

Hi,
What should be the return value of a "type ({b1, b2})"? LRM section 6.23 (Type operator) mentions following text:
The type operator applied to an expression shall represent the self-determined result type of that expression.

But I could not find anywhere self-determined result type defined of an expression.
One of the standard simulators which supports type operator works in its own way.

Here is a sample example:
module top(input bit in1, input bit[31:0] in2, output
        bit [7:0] out1);
        bit [3:0] f0, f1;      
        bit [3:0] l1;
        initial
        begin : blk
                if(type ({f0, f1}) == type (byte))
                        out1 = 1;
                else out1 = 3;
        end
endmodule

-- 
Regards
Surya
    

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