Re: [sv-bc] Type of a concat expression

>From: John Michael Williams <john@svtii.com>

>In verilog, and in the scheduled design constructs of SystemVerilog,
>the "type" of an expression is useless, because
>the way an expression is used determines the meaning of
>the expression.

I agree that this makes the concept of the self-determined type
of an expression less useful in Verilog, but I don't agree that
it is useless. You are exaggerating here.

>Because verilog actively encourages this kind of automatic
>compatibility (implied polymorphism), I see no value to
>permitting the use of type() on an expression -- as opposed
>to on a declared object. An expression isn't even an object,
>in general.

I tend to agree with you that the value is limited, and am
not sure it was that great of an idea to allow it. But the
fact is that it was allowed. The original question was about
its behavior in some areas where the LRM was not entirely
clear. Arguing that it shouldn't have been allowed does not
help answer that original question.

Steven Sharp | Architect | Cadence

P: 508.459.1436 M: 774.535.4149 www.cadence.com

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