NC-Verilog is producing a syntax error for the original example. I did
not investigate to see what steps it took in the expansion to reach that
point. With Greg's alternate definition of the REPEAT macro, NC-Verilog
accepted the example and produced the desired results.
Steven Sharp | Architect | Cadence
P: 508.459.1436 M: 774.535.4149 www.cadence.com
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