Re: [sv-bc] RE: [sv-ac] Identifier usage before declaration in assertion

But LRM say about immediate assertion and which is equivalent to
condition in if statement. So the variable reference
in assertion should be treated in same way as other variable.

-dhiRAj

Korchemny, Dmitry wrote:
>
> I am trying to figure out how the implementation is done. Should this
> be written in the LRM explicitly, is a different question.
>
>
>
> Dmitry
>
>
>
> *From:* Bresticker, Shalom
> *Sent:* Monday, July 12, 2010 10:06 AM
> *To:* Korchemny, Dmitry; Surya Pratik Saha
> *Cc:* ben@systemverilog.us; sv-bc@eda.org; sv-ac@server.eda.org; Adhip Das
> *Subject:* RE: [sv-ac] Identifier usage before declaration in assertion
>
>
>
> But that does not answer the question of why an assertion is
> different. It does not work that way for other constructs. The
> exception is task and function calls, and those ARE described in the LRM.
>
>
>
> Shalom
>
>
>
> *From:* Korchemny, Dmitry
> *Sent:* Monday, July 12, 2010 10:04 AM
> *To:* Surya Pratik Saha
> *Cc:* Bresticker, Shalom; ben@systemverilog.us; sv-bc@eda.org;
> sv-ac@server.eda.org; Adhip Das
> *Subject:* RE: [sv-ac] Identifier usage before declaration in assertion
>
>
>
> Since at the point of this assertion this signal is unknown, it is
> then searched as an XMR. This is my guess, I could not find any
> explicit explanation in the LRM.
>
>
>
> Dmitry
>
>
>
> *From:* Surya Pratik Saha [mailto:spsaha@cal.interrasystems.com]
> *Sent:* Monday, July 12, 2010 10:01 AM
> *To:* Korchemny, Dmitry
> *Cc:* Bresticker, Shalom; ben@systemverilog.us; sv-bc@eda.org;
> sv-ac@server.eda.org; Adhip Das
> *Subject:* Re: [sv-ac] Identifier usage before declaration in assertion
>
>
>
> But why? What is special in assertion or any other scope (I am not
> sure for any other scope similar behaviour is followed or not) for
> that it will be treated as XMR?
>
> Regards
> Surya
>
>
>
> -------- Original Message --------
> Subject: Re:[sv-ac] Identifier usage before declaration in assertion
> From: Korchemny, Dmitry <dmitry.korchemny@intel.com>
> <mailto:dmitry.korchemny@intel.com>
> To: Bresticker, Shalom <shalom.bresticker@intel.com>
> <mailto:shalom.bresticker@intel.com>, ben@systemverilog.us
> <mailto:ben@systemverilog.us> <ben@systemverilog.us>
> <mailto:ben@systemverilog.us>, Surya Pratik Saha
> <spsaha@cal.interrasystems.com> <mailto:spsaha@cal.interrasystems.com>
> Cc: "sv-bc@eda.org" <mailto:sv-bc@eda.org> <sv-bc@eda.org>
> <mailto:sv-bc@eda.org>, "sv-ac@server.eda.org"
> <mailto:sv-ac@server.eda.org> <sv-ac@eda.org> <mailto:sv-ac@eda.org>,
> Adhip Das <adhip@cal.interrasystems.com>
> <mailto:adhip@cal.interrasystems.com>
> Date: Monday, July 12, 2010 12:25:39 PM
>
> I think that in this case aa is treated as XMR.
>
>
>
> Thanks,
>
> Dmitry
>
>
>
> *From:* owner-sv-ac@eda.org <mailto:owner-sv-ac@eda.org>
> [mailto:owner-sv-ac@eda.org] *On Behalf Of *Bresticker, Shalom
> *Sent:* Monday, July 12, 2010 9:54 AM
> *To:* ben@systemverilog.us <mailto:ben@systemverilog.us>; Surya Pratik
> Saha
> *Cc:* sv-bc@eda.org <mailto:sv-bc@eda.org>; sv-ac@server.eda.org
> <mailto:sv-ac@server.eda.org>; Adhip Das
> *Subject:* RE: [sv-ac] Identifier usage before declaration in assertion
>
>
>
> Ben,
>
>
>
> 6.21 says, "A variable declaration shall precede any simple reference
> (non-hierarchical) to that variable."
>
>
>
> Shalom
>
>
>
> *From:* owner-sv-ac@eda.org <mailto:owner-sv-ac@eda.org>
> [mailto:owner-sv-ac@eda.org] *On Behalf Of *ben cohen
> *Sent:* Monday, July 12, 2010 9:31 AM
> *To:* Surya Pratik Saha
> *Cc:* sv-bc@eda.org <mailto:sv-bc@eda.org>; sv-ac@server.eda.org
> <mailto:sv-ac@server.eda.org>; Adhip Das
> *Subject:* Re: [sv-ac] Identifier usage before declaration in assertion
>
>
>
> LRM 3.12 Compilation and elaboration addresses the elaboration.
>
> Elaboration takes care of the variables being declared in the design.
> LRM: "Not all syntax and semantics can be checked during
>
> the compilation process."
>
> Ben Cohen
>
> On Sun, Jul 11, 2010 at 11:21 PM, Surya Pratik Saha
> <spsaha@cal.interrasystems.com <mailto:spsaha@cal.interrasystems.com>>
> wrote:
>
> Hi,
> For the following case:
> module top(input clk, input [3:0] iT, output [3:0] oT);
> assert property (@(posedge clk) (aa == 4'b0000)) ;
> reg [3:0] aa;
> always @(posedge clk)
> aa <= iT;
> assign oT = aa;
> endmodule // top
>
> All the standard simulators pass the case. Please note that 'aa' is
> used before it is declaration in the assertion statement. I could not
> find any text in the LRM regarding this. What is the reason of this?
>
> --
> Regards
> Surya
>
>
>
>
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