[sv-bc] The Verilog Preprocessor: Force for `Good and `Evil

FYI: This is the abstract of a paper to be presented at Boston SNUG on Sept 21.

The Verilog Preprocessor: Force for `Good and `Evil
Wilson Synder [Cavium Networks]

Join an exploration of some fun and horrid usages of the Verilog Preprocessor, and learn best practices from them. Including: Good and bad message and assertion macros, using `line in generated code, the mystery of where comments land, and the localparam-vs-function-vs-define trade-offs. We then consider metaprogramming with defines, to build `if, `for, lookup tables and hashes inside the preprocessor, and use includes as a template language. We present vppreproc, an open-source 1800-2009 preprocessor, and how to leverage it for custom scripts. We conclude with a wrap up of vendor preprocessor compatibility

Shalom Bresticker
Intel LAD DA, Jerusalem, Israel
+972 2 589 6582 (office)
+972 54 721 1033 (cell)
http://www.linkedin.com/in/shalombresticker

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