[sv-bc] Explicit non-ANSI port declarations

Hi,

The Verilog standard used to say about non-ANSI port declarations:

"Each port_expression in the list of ports for the module declaration shall also be declared in the body of the module as one of the following port declarations: input, output, or inout (bidirectional)."

The syntax was

list_of_ports ::= ( port { , port } )

port ::=
  [ port_expression ]
| . port_identifier ( [ port_expression ] )

port_expression ::=
  port_reference
| { port_reference { , port_reference } }

port_reference ::=
  port_identifier
| port_identifier [ constant_expression ]
| port_identifier [ range_expression ]

Then it was pointed out that one does not make a port declaration for the port_expression. The port_expression can be a concatenation or a vector select.

So "port_expression" was changed to "port_identifier" in 1364-2005.

But now this is wrong for explicit port declarations.

An explicit port declaration looks like this:

module m( .a(b) ) ;

where a is the port name and b is an internal signal that connects to the port.
The port declaration needs to be on b, not on a.

So the text is now incorrect.
It needs to say something like "Each port_identifier in the port_expressions in the list of ports..."

Shalom

Shalom Bresticker
Intel LAD DA, Jerusalem, Israel
+972 2 589 6582 (office)
+972 54 721 1033 (cell)
http://www.linkedin.com/in/shalombresticker

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