[sv-bc] Illustration of abstract class mechanism to connect to DUT

From: Rich, Dave <Dave_Rich@mentor.com>
Date: Mon Sep 13 2010 - 10:46:30 PDT

The link below is to a thread that discusses the alternative mechanism
to connecting a testbench to a DUT.

post #2 has the paper, posts #10 and #13 have examples.

http://ovmworld.org/forums/showthread.php?100-OVM-wrapper-for-Verilog-Bf
ms

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.

Received on Mon Sep 13 10:46:57 2010

This message: [ Message body ]
Next message: Rich, Dave: "RE: [sv-bc] Is number assigned to generate block reset at the end of design unit"
Previous message: Bresticker, Shalom: "RE: [sv-bc] Is number assigned to generate block reset at the end of design unit"

Contemporary messages sorted: [ By Date ] [ By Thread ] [ By Subject ] [ By Author ] [ By messages with attachments ]

This archive was generated by hypermail 2.1.8 : Mon Sep 13 2010 - 10:49:34 PDT