[sv-bc] Interfaces in port lists

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-------- Original Message --------
Date: Thu, 16 Sep 2010 08:17:54 -0500
From: Keithan <james@keithan.com>
To: "sv-ec@eda.org" <sv-ec@eda.org>
Subject: Interfaces in port lists

Folks,
   A question about parameterized interfaces in a module port list.
   It is my understanding that the following is the SV way to use
   interfaces in module port lists:

   interface A #( int unsigned WIDTH = 32);
     logic[WIDTH-1:0] a;
     logic[WIDTH-1:0] b;
     modport o_a(
        output a,
        input b);
     modport i_a(
        input a,
        output b);
   endinterface

   module B (interface b); // this works
     // use example
     initial b.a <= 1;
     initial b.c <= 0; // this will compile?
   endmodule

   module C (A#(16) c); // This does not compile
   //
   endmodule

The question is, why can't you declare an interface
[and parameter] [and modport]
in the port list directly? It is a fully qualified type. The corollary
doesn't this introduce virtual interfaces into modules? Is this good?

How does the compiler resolve interface pin references (ex. b.a)
with just the 'interface' type? Doesn't this only get resolved
at load time?

My objective here is to use interfaces in module port lists
to simplify connections and catch directional issues early,
through the use or modports. It does not seem that is the case
with the 'interface' key word.

James Keithan

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