[sv-bc] Re: [sv-ac] Simulation semantics of continuous assignment

Hi.

If SV is consistent with verilog on this (and it
should be), a continuous assignment would be
executed only in the active region. It's a wire
update, not a reg update.

The evaluation of the RHS depends on the way the program block
(I assume you mean a procedural assignment) was written.
For example, a nonblocking assignment to a RHS variable would
not be moved to the active region until the active region was
emptied during the preceding cycle. Only after the nonblocking
statement was executed would the RHS be updated and therefore
the cts assignment (statement) be moved to the active region
for execution.

Variables can't be changed except in the active region -- assuming
nothing inconsistent with the verilog event queue.

On 09/21/2010 10:56 AM, Korchemny, Dmitry wrote:
> Hi SV-BC,
>
> We would like to clarify the following question: If there is a continuous assignment in a module, and its RHS was modified in a program block, when will this continuous assignment be evaluated - in the Active or in the Reactive region? Where is this described in the LRM?
>
> 4.9.1 "Continuous assignment" is not very clear about it. To me it looks like that since the event is scheduled in the Reactive region, it should be evaluated there. So if there is a continuous assignment whose RHS depends both on design and TB elements, it can be evaluated both in the Active and Reactive regions. Though I may be mistaken.
>
> Thanks,
> Dmitry
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