[sv-bc] Is wild equality/inequality operator allowed on aggregate expression?

  Hi,
Is wild equality/inequality operator allowed on aggregate expression? I
am getting different results from different standard tools for the
following case?

typedef struct { logic l; } T;
module m;
     T i, j;
     wire o;
     assign o = (i==?j);
endmodule

I did not get any explicit answer from LRM.

-- 
Regards
Surya
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