RE: [sv-bc] assignment pattern to scalar

Hi, Dave.

Thanks for the reminder. I had forgotten that Mantis.

I was surprised to find that all 3 simulators I tested allowed an assignment pattern assignment to a scalar target, though a synthesis tool did not.

Shalom

From: Rich, Dave [mailto:Dave_Rich@mentor.com]
Sent: Monday, October 18, 2010 5:19 PM
To: Bresticker, Shalom; sv-bc@eda.org
Subject: RE: [sv-bc] assignment pattern to scalar

You already reported this as mantis 2708 last year.

 I believe the LRM says that each set of braces matches each dimension of the array. In this case there are no dimentions, so no braces should be allowed.

However, intentionally or unintentially, some implementations have allowed references to a[0:0] to be the same as a reference to a scalar a. That needs to be resolved first.

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Bresticker, Shalom
Sent: Monday, October 18, 2010 3:10 AM
To: sv-bc@eda.org
Subject: [sv-bc] assignment pattern to scalar

Is the following legal?

logic a;
always_comb a = '{default:'1};

Thanks,
Shalom

Shalom Bresticker
Intel LAD DA, Jerusalem, Israel
+972 2 589 6582 (office)
+972 54 721 1033 (cell)
http://www.linkedin.com/in/shalombresticker

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