[sv-bc] ANSI vs. non-ANSI explicitly named ports

Hi,

Both ANSI and non-ANSI port declaration styles allow explicitly named ports, but they seem inconsistent to me.

The explicitly named port declaration has the form

.port_identifier ([port_expression])

For the non-ANSI style, we have the statement in 23.2.2.1,

"Each port_identifier in a port_expression in the list of ports for the module declaration shall also be declared in the body of the module as one of the following port declarations: input, output, inout (bidirectional), ref, or as an interface port (see Clause 25)."

We have examples like

Example 7-Explicitly named port with mix of input and output directions (non-ANSI style module header)
module mixed_direction (.p({a, e}));
input a; // p contains both input and output directions.
output e;

On the other hand, for ANSI style, we have in 23.2.2.2,

module mymod (
output .P1(r[3:0]),
output .P2(r[7:4]),
ref .Y(x),
input R );
logic [7:0] r;
int x;
...
endmodule

Here it looks like the direction is attached to the port names (P1, P2, Y) and not to the signal names visible inside the module (r,x).

There does not seem to be anything preventing me from writing, for example,

module mymod (
input .P1(r[3:0]),
output .P2(r[7:4]), // r used partly as input and partly as output
input .Y(x),
output .Z(x) ); // x used both as input and as output
logic [7:0] r;
int x;

In the non-ANSI style, however, the port direction is declared on the internal signal name and not on the external name.

Comments?

Thanks,
Shalom

Shalom Bresticker
Intel LAD DA, Jerusalem, Israel
+972 2 589 6582 (office)
+972 54 721 1033 (cell)
http://www.linkedin.com/in/shalombresticker

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