RE: [sv-bc] module malice( output .name(expr), whatsmytype );

I uploaded a proposal to Mantis 2889 (http://www.eda-stds.org/mantis/view.php?id=2889)

Shalom

From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On Behalf Of Greg Jaxon
Sent: Friday, September 18, 2009 9:57 PM
To: SV_BC List
Subject: [sv-bc] module malice( output .name(expr), whatsmytype );

In section 23.2.2.3 Rules for determining port kind, data type and direction,
the first declaration in a list of port declarations is discussed specially in order to give the defaults
for these port properties.

However, the addition of .named_port(expression) syntax to the ANSI-style port declaration lists
should also effectively reset all the "inheritable" properties except port direction and require subsequent
port declarations to re-establish an inheritable kind and data type.

As written, the LRM implies that the (self-determined) data type of a previous named port would be
available as the default data type going into the next port declared. That is probably not how any
existing systems treat this case. More specification needed.

Greg
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