Subject: RE: [sv-bc] logic -vs- ulogic
From: Jay Lawrence (lawrence@cadence.com)
Date: Tue Sep 16 2003 - 17:31:54 PDT
Mike,
This was discussed in sv-bc meetings. I believe that Cliff Cummings
suggested it.
I have to admit that I voted against the name change. Primarily because
it only solves a small part of the issue with SystemVerilog types.
The "logic" type in SystemVerilog only applies to variables (regs).
Variables are never resolved. So naming it ulogic would imply that there
is also a 'logic' type that is resolved, and there is not.
There is no way in systemVerilog to declare a wire (a resolved object)
of any type (logic, enum, struct, ....).
Were SystemVerilog to address the issue of having wires with a type,
then predefining resolved and unresolved versions might be necessary.
Jay
===================================
Jay Lawrence
Senior Architect
Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================
> -----Original Message-----
> From: Karen Pieper [mailto:Karen.Pieper@synopsys.com]
> Sent: Tuesday, September 16, 2003 6:58 PM
> To: sv-bc@eda.org
> Subject: [sv-bc] logic -vs- ulogic
>
>
> Here is some mail that bounced from Mike Treseler:
>
>
> > >From owner-sv-bc Tue Sep 16 15:04:57 2003
> >Received: from vir2.relay.fluke.com (vir2.relay.fluke.com
> [129.196.184.26])
> > by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id
> > h8GM4s6O007632
> > for <sv-bc@eda.org>; Tue, 16 Sep 2003 15:04:57 -0700 (PDT)
> >Received: from fluke.com ([129.196.180.170] RDNS failed) by
> >vir2.relay.fluke.com with Microsoft SMTPSVC(5.0.2195.5329);
> > Tue, 16 Sep 2003 15:04:50 -0700
> >Message-ID: <3F678902.4040104@fluke.com>
> >Date: Tue, 16 Sep 2003 15:04:50 -0700
> >From: Mike Treseler <tres@fluke.com>
> >Organization: Fluke Networks
> >User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4)
> Gecko/20030624
> >X-Accept-Language: en-us, en
> >MIME-Version: 1.0
> >To: sv-bc@server.eda.org
> >Subject: logic -vs- ulogic
> >Content-Type: text/plain; charset=us-ascii; format=flowed
> >Content-Transfer-Encoding: 7bit
> >X-OriginalArrivalTime: 16 Sep 2003 22:04:50.0977 (UTC)
> >FILETIME=[8D0F4110:01C37C9E]
> >
> >TO: The SystemVerilog Design Committee
> >
> >
> >
> >The SystemVerilog types: "logic" and "bit."
> >ought to be renamed "ulogic" and "ubit."
> >
> >to both clarify that these are unresolved types,
> >and to better match the related VHDL type std_ulogic.
> >
> >
> >
> >
> > -- Mike Treseler
> > Fluke Networks
>
>
>
This archive was generated by hypermail 2b28 : Tue Sep 16 2003 - 17:34:19 PDT