Subject: [sv-bc] logic -vs- ulogic
From: Karen Pieper (Karen.Pieper@synopsys.com)
Date: Tue Sep 16 2003 - 15:57:56 PDT
Here is some mail that bounced from Mike Treseler:
> >From owner-sv-bc Tue Sep 16 15:04:57 2003
>Received: from vir2.relay.fluke.com (vir2.relay.fluke.com [129.196.184.26])
> by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id
> h8GM4s6O007632
> for <sv-bc@eda.org>; Tue, 16 Sep 2003 15:04:57 -0700 (PDT)
>Received: from fluke.com ([129.196.180.170] RDNS failed) by
>vir2.relay.fluke.com with Microsoft SMTPSVC(5.0.2195.5329);
> Tue, 16 Sep 2003 15:04:50 -0700
>Message-ID: <3F678902.4040104@fluke.com>
>Date: Tue, 16 Sep 2003 15:04:50 -0700
>From: Mike Treseler <tres@fluke.com>
>Organization: Fluke Networks
>User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4) Gecko/20030624
>X-Accept-Language: en-us, en
>MIME-Version: 1.0
>To: sv-bc@server.eda.org
>Subject: logic -vs- ulogic
>Content-Type: text/plain; charset=us-ascii; format=flowed
>Content-Transfer-Encoding: 7bit
>X-OriginalArrivalTime: 16 Sep 2003 22:04:50.0977 (UTC)
>FILETIME=[8D0F4110:01C37C9E]
>
>TO: The SystemVerilog Design Committee
>
>
>
>The SystemVerilog types: "logic" and "bit."
>ought to be renamed "ulogic" and "ubit."
>
>to both clarify that these are unresolved types,
>and to better match the related VHDL type std_ulogic.
>
>
>
>
> -- Mike Treseler
> Fluke Networks
This archive was generated by hypermail 2b28 : Tue Sep 16 2003 - 15:59:23 PDT