Re: [sv-bc] Proposals for SV3.1a


Subject: Re: [sv-bc] Proposals for SV3.1a
From: Dave Rich (David.Rich@synopsys.com)
Date: Tue Sep 16 2003 - 07:56:43 PDT


Doug,

Some answers below

Warmke, Doug wrote:

>Dave,
>
>A few questions on SV-BC-49 and SV-BC-48.
>
>1) For the operator overloading, you mention that
> a += operator is automatically built from "+" and "=".
> I didn't get this for a while, but it seems like you are
> saying "If both a unary + and an assignment operator =
> are present for a given function name with identical
> argument type, then the system automatically infers a
> "+=" operator for the given argument type.
> Could you please confirm this, and if true, provide
> an example in the proposal?
>
It is simpler than that. A+=B is rewritten A = A + B, then the
overloading is applied.

>
>2) You state "The overloading statement links + to each function
> prototype according to the argument types, which must match
> exactly." I'm not exactly clear on what must exactly match.
> Do you mean the types of the arguments at the call vs. the
> types of the arguments in the prototype?
>
Yes, this is exactly as is is in C++

>
>3) Also in operator overloading, you mention that DPI
> functions are supported. I assume you mean both
> imported functions (i.e. those declared in SV but
> implemented in C) as well as exported fucntions
> (i.e. implemented in SV, but declared and called from C)
> You should probably emend this to say
> "Note that both imported and exported DPI functions
> are supported by this mechanism."
>

This note is probably not needed because the DPI is supposed to be
invisible from the SV side (i.e the caller is unaware whether it is an
SV or C function actually called).

>
>4) In the flexibility in function description, your more
> complex example seems to be missing any usage of
> primitives-instantiated-as-function-call. I think
> it would be more instructive to add that.
>
The very first example of the wire continuous assignment does this.
*wire* w = a ? *and*(b,c) : *or*(d, *xor*(e,f)); // 1 mux and 3 gates

>
>Thanks,
>Doug Warmke, MTI
>
>
>
>>-----Original Message-----
>>From: Dave Rich [mailto:David.Rich@synopsys.com]
>>Sent: Tuesday, September 16, 2003 12:00 AM
>>To: sv-bc@eda.org
>>Subject: [sv-bc] Proposals for SV3.1a
>>
>>
>>Attached are the proposals for
>>
>>SV-BC-53 Expand array querying functions "arrayq.pdf"
>>SV-BC-37 Interface port expressions "modport expressions.pdf"
>>SV-BC-49 Operator overloading "overload2.pdf"
>>SV-BC-48 Flexibility in Function description and use "function2.pdf"
>>
>>
>>--
>>--
>>David.Rich@Synopsys.com
>>Technical Marketing Consultant
>>http://www.SystemVerilog.org
>>tele: 650-584-4026
>>cell: 510-589-2625
>>
>>
>>
>>
>>
>
>
>
>

-- 
--
David.Rich@Synopsys.com
Technical Marketing Consultant
http://www.SystemVerilog.org
tele:  650-584-4026
cell:  510-589-2625



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