Re: [sv-bc] Generate with multiple begins

Hi Wilson.

Nested begin-ends seem to be legal in verilog 2005
(1364 Section 12.4.1 Example 5 -- under control of
for, rather than if).

I don't see any special problem with the hierarchy,

t.g1.g2
t.g1.g3

so it should be possible to generate it.

The BNF of the grammar may indeed be incomplete.

On 01/09/2011 06:24 PM, Wilson Snyder wrote:
>
> Hello all,
>
> I have a user that sent me the following case which seems to
> work on several simulators, but I don't see that nested
> begin/ends are legal in generates according to the 2009
> grammar. Is this an oversight in the grammar, or intended
> to fail? Can someone clarify please? Thanks!
>
> module t;
> generate
> if (1) begin : g1
> begin : g2
> initial $display("Hello");
> end
> begin : g3
> initial $display("World");
> end
> end
> endgenerate
> endmodule
>
> My reading of the grammar is thus:
>
> loop_generate_construct ::=
> FOR '(' ... ')' generate_block
>
> generate_block ::=
> generate_item
> | [ generate_block_identifier ':' ] BEGIN [ ':' generate_block_identifier ]
> { generate_item }
> yEND [ ':' generate_block_identifier ]
>
> generate_item ::=
> module_or_generate_item
> | interface_or_generate_item
> | checker_or_generate_item
>
> None of these three _item's have a path back to
> generate_block without hitting another generate
> if/case/for.
>
> Looking at it from the bottom up, the only relevant rules which use the
> begin/end keywords are seq_block and generate_block.
>
> generate_block called from
> loop_generate_construct,
> if_generate_construct,
> case_generate_item
>
> seq_block called from
> statement_item
>
> We're not in a statement, so begin must be preceeded by
> loop/if/case; there's no direct path from generate_item
> (etc).
>
> Thanks
>

-- 
         John Michael Williams
         jwill@BasicISP.net
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