Re: [sv-bc] Generate with multiple begins

Hi Brad,
VHDL-2008 added elsif and else to an if generate.
It also added case generate.

Best,
Jim

> What's wrong with generate-else? We use them all the time.
>
> Shalom
>
>> -----Original Message-----
>> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
>> Brad Pierce
>> Sent: Monday, January 10, 2011 10:44 PM
>> To: sv-bc@eda.org
>> Subject: RE: [sv-bc] Generate with multiple begins
>>
>> When Verilog-2001 added the generate construct, it allowed generate-
>> else clauses, and I'm suggesting it would have been better to stick
>> with the tried-and-true restrictions of VHDL. But, of course, it's too
>> late to undo generate-else.
>>
>> -- Brad
>
> ---------------------------------------------------------------------
> Intel Israel (74) Limited
>

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Jim Lewis
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