I polled internally at AMD and uncovered the following 5 use cases where language support for configurable module port lists would be useful:
1. Modules that need different views (RTL, DFT) at different points in the design cycle. Additional ports are added as the view is refined. A typical case might be a flip-flop with or without scan ports.
2. Modules that appear multiple times in the design with different ports. This can happen when different generations of a common module are used in different parts of an SoC.
3. Modules that appear in multiple SoCs in the same family, with differences controlled by per-design features. Here the desire is to maintain a single codebase for all variants.
4. Modules that might have the same types of ports, but where the port names are changed to indicate the actual client. This customizes the design to make debugging / tracing of signals easier.
5. Modules that have lists of ports with indexed names, because a parameterized port array cannot be or is not used for other reasons.
I think generated ports/connections would be usable in the first 3 cases. The second case really isn't possible to cover using a global `ifdef, but I believe the SV configuration mechanism could be used to alias two different modules to the same name in different parts of a design. For the 4th & 5th cases, you'd need a more complex interaction between the SV lexer/parser, such that a parsed parameter can modify a lexical name. I don't think generate would solve that.
Largely through the use of external preprocessors (aka language extensions), all 5 of these use cases appear within AMD designs, some of them extensively.
One other note: although the description doesn't state this, a followup comment makes it clear you'll need generate for module instantiations as well to take advantage of this language change.
~ Dave
// David A. Gates, Ph.D. 408.749.4497
// Fellow, Design Automation
// Advanced Micro Devices www.amd.com<http://www.amd.com/>
// The Doctor is IN. Primum non nocere.
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