RE: [sv-bc] Bit/Part select of modport named argument

You could certainly base this on whether an operator has been applied, rather than its being used in an expression. The question is whether SV does that. Please provide any example where something inherits a type from the type of an expression, and where the LRM clearly specifies that it can inherit the shape of packed dimensions.

I have provided the example of untyped parameters inheriting their type from the type of an integral expression, and the LRM clearly specifies that the result is a simple vector.

-----Original Message-----
From: Greg Jaxon [mailto:Greg.Jaxon@synopsys.com]
Sent: Tuesday, February 08, 2011 11:06 AM
To: Steven Sharp
Cc: brad_pierce@acm.org; Surya Pratik Saha; sv-bc@eda.org
Subject: Re: [sv-bc] Bit/Part select of modport named argument

On 2/7/2011 1:20 PM, Steven Sharp wrote:
> interface iface;
> logic [2:0] [2:0] [2:0] x;
> modport mport (input .j (x));
> endinterface
>
> The type of the identifier x is a 3-dimensional packed array. The self-determined type of the port expression x is a 27-bit vector.

I disagree.

If you'd said x+1'b1, I'd agree; + ignores x's shape, but until that shape is consumed somewhere, it is the part of the self-determined type of any reference to x.

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