RE: [sv-bc] Bit/Part select of modport named argument

Interestingly, 20.7 says,

"$dimensions shall return the following:
- The total number of dimensions in the array (packed and unpacked, static or dynamic)
- 1 for the string data type or any other nonarray type that is equivalent to a simple bit vector
type (see 6.11.1)"

6.11.1 says,

"The term simple bit vector type is used throughout this standard to refer to the data types that can directly
represent a one-dimensional packed array of bits. The integer types listed in Table 6-8 are simple bit vector
types with predefined widths."

and Table 6-8 includes logic, reg, and bit.

So according to the LRM, $dimensions(x) should return 1 where x is declared as a simple scalar of type logic.

When I tried this on several simulators, each gave me a different answer.
One returned 1, one returned 0, and the third gave an error, saying that the argument had to be an array_identifier.

Shalom

> -----Original Message-----
> From: Steven Sharp [mailto:sharp@cadence.com]
> Sent: Wednesday, February 09, 2011 5:37 AM
> To: Bresticker, Shalom; brad_pierce@acm.org
> Cc: Surya Pratik Saha; sv-bc@eda.org
> Subject: RE: [sv-bc] Bit/Part select of modport named argument
>
> If x is declared as an unpacked array of ints, then the type of x[0] is
> definitely not an unpacked array. An unpacked array cannot be used in
> an integral expression, and x[0] can. The self-determined type of x[0]
> is the same as an int.
>
> But you cannot extrapolate from the rules for unpacked arrays to
> resolve this question about packed arrays. If x is declared as a
> packed array, then you can use both x and x[0] in the same integral
> expression. Trying to extrapolate the rules for packed types from the
> rules for unpacked types would have suggested otherwise. The rules for
> integral types are different from the rules for unpacked types, and
> cannot be extrapolated from them.
>
> I am not aware of any test that can be applied to an expression, where
> the LRM clearly specifies a different result for a scalar and a 1-bit
> vector. You can apply a bit-select to a variable or net to determine
> whether it is a scalar (in which case it is an error) or a vector (in
> which case it is legal). But you cannot apply a bit-select to an
> expression, unless it is a concatenation. And in that case, the LRM
> specifies the same result whether the thing in the concatenation is a
> scalar or a 1-bit vector.
>
>
> That doesn't mean that some construct (such as applying a bit select to
> a modport named argument) couldn't treat them differently. But I don't
> see anything in the LRM that specifies that it does. And it does mean
> that there is no precedent for it doing so.
>
>
> -----Original Message-----
> From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com]
> Sent: Tuesday, February 08, 2011 10:35 AM
> To: Steven Sharp; brad_pierce@acm.org
> Cc: Surya Pratik Saha; sv-bc@eda.org
> Subject: RE: [sv-bc] Bit/Part select of modport named argument
>
> So the type of j is a vector because it takes the type of the
> expression in the parentheses, and the type of x[0] when used as an
> expression is a 1-bit vector.
>
> On the other hand, the type of x[0] itself would seem to be a scalar.
> Suppose x was declared not as a packed array, but rather as an unpacked
> array. One would not want x[0], a select of a single element, to be
> considered an unpacked array of a single element. That would prevent it
> from being used in many contexts without casting. So a single element
> select should have the type of the element. It would seem consistent
> for that to be the same also if the array were packed. So the type of
> x[0] should be simply 'logic'.
>
> Shalom
>
> > -----Original Message-----
> > From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
> > Steven Sharp
> > Sent: Monday, February 07, 2011 9:45 PM
> > To: brad_pierce@acm.org
> > Cc: Surya Pratik Saha; sv-bc@eda.org
> > Subject: RE: [sv-bc] Bit/Part select of modport named argument
> >
> > Also compare with the rules for parameters declared without a type,
> > which get their type from the expression which is assigned to them,
> > just like these ports. The LRM says "If the expression is integral,
> > the parameter is a logic vector of the same size with range [size-
> > 1:0]." If the integral expression were a bit select like x[i], the
> > result would still be a vector, with size 1, and the range [0:0].

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