RE: [sv-bc] streaming operator unpack doubt

Hi,

I tested this on a couple of simulators and got different results.

One gave me

c=z0x
c=0z1

and another gave me

c=1z0
c=x0z

Shalom

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Daniel Mlynek
Sent: Friday, February 11, 2011 11:10 AM
To: Rich, Dave
Cc: Steven Sharp; Arturo Salz; sv-bc@eda.org
Subject: Re: [sv-bc] streaming operator unpack doubt

so could you tell what should be the result in my example, after I've fixed d into c var as below:
module top;
reg [4:1] b1;
reg [3:1] c;
initial
begin
    #1 b1='b1z0x;
      {>>{c}} =b1; $display("c=%b ",c);
    #1 b1='b1z0x;
      {<<{c}} =b1; $display("c=%b ",c);
end
endmodule

On 2/11/2011 2:00 AM, Rich, Dave wrote:
'If the source expression contains more bits than are needed, the appropriate number of bits shall be consumed from its left (most significant) end."

I believe 'its' is referring to the source expression, before re-ordering. After re-ordering is no longer the source expression.
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.