Re: [sv-bc] Query regarding the usage of implicit generate block name in hierarchical reference

Hello Harpeet,

The testcase in your example is illegal.

According to LRM 1800-2009,section 23.9

"If an identifier is referenced with a hierarchical name, the path can
start with a module name, interface name,
program name, checker name, instance name, task, function, named block,
or named generate block."

And according to section 23.6 says

"Unnamed generate blocks are exceptions. They create branches that are
visible only from within the block and
within any hierarchy instantiated by the block."

also
"Objects declared in unnamed generate blocks are also exceptions. They
can be referenced by hierarchical names only from within the block and
within any hierarchy instantiated by the block."

And to reference the element withing the block,no hierarchical name is
required as it's directly visible.

Regards,
dhiRAj
 

Harpreet Singh Anand wrote:
>
> Hi,
>
>
>
> I have query regarding the usage of implicit generate block (created
> for unnamed block) in hierarchical references. The LRM, says,
>
>
>
> "Although an unnamed generate block has no name that can be used in a
> hierarchical name, it needs to have a name by which external
> interfaces can refer to it."
>
>
>
> My queries are:
>
> 1) Can we use implicit names in hierarchical references.
>
> 2) What does "external interfaces" mean? Is it like representing
> complete hierarchy and things like that
>
>
>
> Example:
>
>
>
> module test (input [7:0] in, input clk, output [7:0] out1);
>
> genvar i;
>
> generate
>
> for(i=0; i < 8; i = i+1)
>
> begin
>
> flop my_flop(in[i], clk, out1[i]);
>
> defparam *genblk1*[i].my_flop.P1 = i; // Is this usage
> of implicit names (*genblk1*) valid
>
> end
>
> endgenerate
>
> endmodule
>
>
>
>
>
> Thanks & Regards,
>
> Harpreet Singh
>
>
>
>
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