[sv-bc] RE: Query regarding the usage of implicit generate block name in hierarchical reference

________________________________
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Harpreet Singh Anand
Sent: Tuesday, March 22, 2011 2:34 AM
To: sv-bc@eda.org
Cc: Harpreet Singh Anand
Subject: [sv-bc] Query regarding the usage of implicit generate block name in hierarchical reference

Hi,

I have query regarding the usage of implicit generate block (created for unnamed block) in hierarchical references. The LRM, says,

"Although an unnamed generate block has no name that can be used in a hierarchical name, it needs to have a name by which external interfaces can refer to it."

My queries are:

1) Can we use implicit names in hierarchical references.

As stated in the text you just quoted above, "an unnamed generate block has no name that can be used in a hierarchical name," so clearly this name cannot be used in a hierarchical reference.

2) What does "external interfaces" mean? Is it like representing complete hierarchy and things like that

PLI, VCD output, simulator user interfaces and so forth. All of them things outside the Verilog language.

Example:

module test (input [7:0] in, input clk, output [7:0] out1);
 genvar i;
 generate
 for(i=0; i < 8; i = i+1)
 begin
                flop my_flop(in[i], clk, out1[i]);
                defparam genblk1[i].my_flop.P1 = i; // Is this usage of implicit names (genblk1) valid
 end
 endgenerate
endmodule

Illegal. Also unnecessary in this case, since you can simply refer to my_flop directly from here. If you wanted to refer to it from outside the generate block, you would need to give the generate block a name.

 Thanks & Regards,
Harpreet Singh

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