[sv-bc] Collapsing semantics for user-defined composite nets

I'm sending this out broadly to gather input regarding some decisions
that the SV-DC committee needs to make regarding collapsing
semantics and implications of that for user-defined composite nets.

If you have input and due to participation rules cannot respond
to the reflector, you can respond directly with feedback to either
Scott or myself (both cc'd here).

Background

The basic mandate of SV-DC is to propose enhancements to SV to
allow for more flexible pure digital models which can more reasonably
approximate analog subsystems. As part of that work, SV-DC is first
proposing extensions to allow "atomic" composite nets and user
defined resolution functions for such nets. This is conceptually similar
to VHDL's composite signal support with user defined resolution.

Current status

There is a reasonable level of consensus on the basics of the proposal
including how atomic composite nets and resolution functions are
to be defined. There is also consensus that such nets should
collapse across inout port connections. This is important to
make a requirement since user-define resolution functions might
often be non-associative and require all drivers to be presented
in order to correctly compute a resolved value on the net.

The main question within the committee is whether collapsing
should be required across input and output ports as well. Doing
so would be at least philosophically more consistent with
collapsing expectations in existing verilog. However, requiring
input and output ports to not collapse would provide a second
form of resolution under (indirect) user control -- full collapsed
driver presentation for inout connected nets and a more
hierarchical segmented approach (similar to VHDL) when input
or output port boundaries are encountered.

While there are certainly resolution function definitions which
could demonstrate the difference with a hierarchical resolution
(such as a simple "average" taking the sum of driven values
divided by the number of drivers), it is not clear whether there
are any situations in which hierarchical resolution would in fact
be semantically preferable to the fully collapsed view. If there is not,
it would likely be preferable to not bother supporting a "hierarchical"
resolution flow via port modes and simply require full collapsing
in all cases.

This is not a trivial decision as it impacts future compatibility
no matter what we do and also potentially impacts discussions
regarding alignment of Verilog-AMS and SV. We are talking
directly to the Verilog-AMS committee as well, but wanted to
attempt to have as broad an audience as possible.

The current proposal can be review via mantis at:
     http://www.eda.org/svdb/view.php?id=3398

If you do have feedback or would like clarifications, please feel
free to contact me (or Scott) and we can coordinate discussion.

For longer discussion responses, it is likely better to just respond
to sv-dc in order to reduce noise in sv-ec/sv-bc. Those who would
like to monitor any discussion should probably watch the sv-dc
archive.

Thanks all.

Gord.

-- 
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com
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