Re: [sv-bc] mantis item 3608

On 6/14/2011 10:26 AM, Francoise Martinolle wrote:
> In Verilog no forward references where allowed for any data object.
> With the introduction of type parameters, resolving a name or a dotted name defers the resolution until
> elaboration. At that point, the symbol tables are filled in and a simple look up mechanism may
> find declarations after use.

Type parameters did not change any rules regarding look-ups in the name spaces where the root of the dotted name is resolved.
Neither your example 1 nor 2 is legal because the name w has no referent at the point of its first use.

Names in these positions are able to cause package wildcard import, which happens long before elaboration even begins.

Greg

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