[sv-bc] RE: Evaluating bounds in array declarations

As you say, the issue far predates SV. Originally it would have come from Verilog-XL. Here are the answers to your examples based on XL.

Wire w1 has 2 bits, and wire w2 has 1 bit.

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Brad Pierce
Sent: Monday, June 27, 2011 3:41 PM
To: sv-bc
Subject: [sv-bc] Evaluating bounds in array declarations

In an array declaration, such as

         wire [constant_expression : 0] w;

is the constant_expression

     1) statically cast to 'integer' in the SV style (that is, evaluated in the context of an assignment to the signed type 'integer'), or
     2) evaluated in a self-determined context and used as is (possibly unsigned), or
     3) evaluated in a self-determined context, but then cast to an integer?

I'm guessing 3, but don't find an answer in the LRM. Why 3? Because the issue far predates SV and its static cast, and the result of self-determined context used as-is leads to strange results.

For example, does the following have 2 bits, or a huge number of bits?

       wire [ 32'b0 - 1 : 0] w1; // type(32'b0 - 1) is unsigned

For example, does the following have 7 bits or 1 bit?

       wire [ 1'b1 + 1'b1 + 1'b1 << 1 : 0] w2; // 6 == (1'b1 + 1'b1 + 1'b1 << 1)

-- Brad

--
This message has been scanned for viruses and
dangerous content by MailScanner<http://www.mailscanner.info/>, and is
believed to be clean.
-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.