[sv-bc] variable driven by continous assignment and ref port

IMHO LRM is not explicit for below case. Should it be error if variable
is driven by both continous assignment and ref port of function (ref
port of module)?
I assume that const ref should be ok.

    module bench ;
         reg packetbanch = 0;
         bit valid ;
         initial #5 packetbanch=1;
         initial #6 packetbanch=0;
         test chk1( packetbanch, valid) ;
    endmodule

    function automatic bit crc(ref reg packetcrc ) ;
      //packetcrc = 1;
      return 1'b0;
    endfunction

    module test ( input reg packet, output bit valid ) ;

    initial begin
       $monitor("%d> %d %d", $time, packet, bench.packetbanch);
       #1;
       if (crc( packet ) == 1'b1) // error packet is driven by both
    continous and procedural assign???
       valid = 1'b1 ;
       #10;
       $finish;
      end
    endmodule

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