Re: [sv-bc] nettype

thx for explanation.
I understand the current state and current proposal for nettype I was
just thinking that nettype will be working the way I've describe it here..

DANiel

On 12/5/2011 5:06 PM, Gordon Vreugdenhil wrote:
> Daniel,
>
> You are trying to treat "wire" as part of the type. But that isn't
> the way that the LRM treats "wire" at all. As just one example,
> "wire" isn't a type that can be passed through a type parameter. The
> nettype change is not intended to change that kind of relationship.
> "nettype" works in a manner that is the same as "wire" -- the kind of
> the declaration (variable, wire, nettype, etc) isn't part of the type,
> it is related to the object being declared. So one can parameterize
> the data type, but not the kind of the declaration.
>
> In your example, you certainly can have:
> wire mytype w;
> and in fact if you have a parameterized module, you could have:
>
> module m #(type T);
> wire T w;
> endmodule
>
> But there is no way to parameterize the wire/variable decision.
>
> The nettype work is not intended to address what I think you are
> requesting. User defined nettypes merely provide a symmetric
> mechanism as "wire" but with more interesting data types for each "pin".
>
> Gord.
>
> On 12/5/2011 6:39 AM, Daniel Mlynek wrote:
>> No i want simple feature equals to what can I do for data types.
>> Ie I want do declare a net with a data type and predefined net type
>>
>> wire logic [3:0] w;
>>
>> Assume that I'm using such pair in many places and I want to change
>> the net type - to do so I would have to find each interesting
>> occurrence and do the change is I could :
>>
>> typedef_net wire mynet;
>> typedef reg[3:0] mytype;
>> mynet mytype w;
>>
>> then all I need to do is to change mynet declaration.
>>
>> Same idea like for types
>>
>>
>>
>> DANiel
>>
>>
>> On 12/5/2011 3:26 PM, Francoise Martinolle wrote:
>>> I am trying to understand what you want to achieve.
>>> Do you want to "redefine' the already predefined nettype "wire" and
>>> use its
>>> predefined resolution for the logic datatype?
>>>
>>> Francoise
>>> '
>>>
>>> -----Original Message-----
>>> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
>>> Daniel Mlynek
>>> Sent: Wednesday, November 30, 2011 3:09 AM
>>> To: sv-bc@eda.org
>>> Subject: [sv-bc] nettype
>>>
>>> sv2012 adds nettype: mantis: 3398 . Extension define in this mantis
>>> add more possibilities but I was thinking about smth simpler.
>>> Now I do not have a way to define smth like typedef on net_type to
>>> achieve declaration like:
>>>
>>> typedef_net wire mynet;
>>> typedef reg[3:0] mytype;
>>> mynet mytype w;
>>>
>>> mantis 3398 will also wont help me.
>>>
>>> DANiel
>>>
>>>
>>> --
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>>>
>>>
>>
>

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