[sv-bc] RE: unsized parameter values

I covered most of this in my response to Mark's email. Now I will address Surya's question directly.

The size of an unsized constant number is 32 bits in SV (or an implementation-dependent size equal to an integer variable in Verilog). It doesn't matter whether it is used in a self-determined or context-determined expression. It is 32 bits either way. It doesn't change size any more than an integer variable changes size depending on the expression it is used in.

If the constant is used in a wider expression, then the 32-bit value of the constant is zero-extended or sign-extended to the size of the expression, just as a 32-bit integer variable is zero-extended or sign-extended to the size of the expression. It isn't extended from secret hidden value bits that were invisible in a self-determined context for some reason.

A decent tool should tell you that it is truncating the excess bits you specified in your unsized constant, to fit into the 32-bit size of the constant, just as it should if you specified the size explicitly with 32'b01... After truncation, those bits are gone, since they aren't part of the value of the 32-bit constant. You can't get them back by using the constant in a wider context-determined expression, any more than you can recover bits truncated during an assignment to an integer variable by using that variable in a wider expression.

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Maidment, Matthew R
Sent: Thursday, June 21, 2012 6:10 PM
To: sv-bc@eda.org
Subject: [sv-bc] unsized parameter values

Sending this for Surya:

Hi,
I have a query on unsized parameter value propagation with more than 32 bits value. Please consider the following case, where there are two parameter declarations, one has no range or type specification overridden by unsized based number. Other one is overridden by the previous parameter.

module top;
    A #(36, 'b010001110111011101110111011101110111) iA();

    initial begin
        $display(" parameter values :: iA.p_a %b , iA.iB.p_b %b ", iA.p_a, iA.iB.p_b);
    end
endmodule

module A;
    parameter w = 2;
    parameter p_a = 'b00100;
    reg [w:0] a;

    B #(w, p_a) iB();

endmodule

module B;
    parameter w = 5;
    parameter [(w-1) : 0] p_b = 'b001;
    reg [w:0] a;

endmodule

I know, in the context insensitive places, the unsized expression width becomes same as integer (32), otherwise it should take the size of the context. With that respect, the $display value should print '010001110111011101110111011101110111' for both. But one standard simulator truncates the 'iA.p_a' value to 32 bit and then prints. Though other two shows the result as I understood. What should be the expected result.

Regards
Surya
Received on Thu Jun 21 17:36:50 2012