[sv-bc] RE: Query related with signedness of an expression.

Hello Surya,

Thanks and I have notice that section but the section says about packed array declaration. So will it be applicable for packed array declaration through multilevel typedef ??

as reg4 can't be equivalent to 'typedef reg signed [1:0][1:0] reg4_n;'  because in previous case var1[1] is signed but var1 declared with type of 'reg4_n', then var1[1] is unsigned.

Regards,
dhiRAj




From: Surya Pratik Saha [mailto:surya.pratik.saha@xilinx.com]
Sent: Friday, November 16, 2012 2:04 PM
To: Dhiraj Kumar Prasad; sv-bc@eda.org
Subject: RE: Query related with signedness of an expression.

Hi Dhiraj,
SV 2009 LRM mentioned (page 103):
If a packed array is declared as signed, then the array viewed as a single vector shall be signed. The individual
elements of the array are unsigned unless they are of a named type declared as signed. A part-select of a
packed array shall be unsigned.

Hence 'var1' has to be treated as signed.

Regards
Surya

From: owner-sv-bc@eda.org<mailto:owner-sv-bc@eda.org> [mailto:owner-sv-bc@eda.org] On Behalf Of Dhiraj Kumar Prasad
Sent: 16 November 2012 13:57
To: sv-bc@eda.org<mailto:sv-bc@eda.org>
Cc: Dhiraj Kumar Prasad
Subject: [sv-bc] Query related with signedness of an expression.

Hello,

I have an query related with signedness of the expression.

Please see the following example

module top(output reg [7:0] out1);

typedef reg signed [1:0] reg2;
typedef reg2 [1:0] reg4;

reg4 var1;

always_comb
begin
        var1 = '1;
        out1 = var1;
end
endmodule

Here the var1 should be treated as signed or unsigned. I am seeing the different result in different standard tools. Some tool's are assigning out1 with 8'b11111111 (treated as signed) while some other tools are assigning out1 with 8'b00001111.

So my query is should var1 be treated as signed or unsigned ??

Regards,
dhiRAj


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