[sv-bc] RE: DAC Presentation of SV-2012 Enhancements - Cliff requests your input

Cliff,
Here is my list:
1 - Interface classes: These are very useful as they allow developers to declare abstract types whose functionality can be implemented by subsequent layers. They can simulate multiple inheritance (without many of the problems). I expect them to become very important in the specification of protocols and reusable verification infrastructure. An important use of interface classes is their ability to use an object with no knowledge about its type, only that it implements a particular interface.
2- Soft constrains: This class of constrains fill a void in the previous standard that complicated the specification of default values, and default distributions.
3- Nettypes (Generic interconnects) - Nettypes bring a much needed feature to the language: the ability to declare nets of arbitrary user-defined types that support multiple drivers. This feature will enable the modeling of high-performance (i.e. event-driven) analog models. Generic interconnects together with nettypes enable in a scalable fashion the definition and use of different models without the need to change the overall design - only the leaf cells.
                Arturo

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Bresticker, Shalom
Sent: Wednesday, May 29, 2013 10:50 AM
To: sv-ac@eda.org; sv-bc@eda.org; sv-cc@eda.org; sv-ec@eda.org; sv-dc@eda.org; IEEE P1800 Working Group (ieee1800@eda.org)
Cc: Clifford E. Cummings (cliffc@sunburst-design.com)
Subject: [sv-bc] FW: DAC Presentation of SV-2012 Enhancements - Cliff requests your input

Hi,
Cliff Cummings asked me to forward this.
Shalom
From: Clifford E. Cummings [mailto:cliffc@sunburst-design.com]
Sent: Wednesday, May 29, 2013 20:46
To: Bresticker, Shalom
Subject: DAC Presentation of SV-2012 Enhancements - Cliff requests your input

Hi, All -

I have been asked to give a short SystemVerilog-2012 update presentation at DAC. Stu Sutherland has already done a nice update last year at DAC but I would like to take a slightly different approach while sill acknowledging and referencing his DAC presentation.

I would like to gather input from as many SystemVerilog-2012 committee members as a I can regarding your favorite SystemVerilog-2012 enhancements. I would suggest that you email me with your five favorite enhancements (feel free to send fewer or more than five favorites).

Everyone that sends me a small list of favorites will be acknowledged and thanked in my presentation, which will eventually go into the public domain and will also be posted on my web page.

Time is short! All I need is a list of your favorite enhancements, preferably by the end of day on Friday, but you get extra credit for the following:
(1) Why each enhancement is on your favorites list.
(2) Any examples that show why the enhancement is cool!
(3) Reference to specific section numbers of the IEEE 1800-2012 LRM.

This is your chance to highlight enhancements that you as a committee member felt was important to the Design and Verification community.

Thanks in advance for you short (or extended) feedback.

If anybody has a complete list of the enhancements that was compiled separate from Stu's list, you get double-extra credit!

Regards - Cliff
--
Cliff Cummings - Sunburst Design, Inc. 1639 E. 1320 S., Provo, UT 84606 - 801-960-1996- cliffc@sunburst-design.com<mailto:cliffc@sunburst-design.com> / www.sunburst-design.com<http://www.sunburst-design.com> World Class Verilog, SystemVerilog & OVM/UVM Training

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