[sv-bc] 0003605: UVM ubus example should not use controversial code with variable driven by mix of continous assignment and procedural assign

Question for the sv-bc team from a UVM bug that I own.

Daniel Mlynek filed this UVM Users Guide bug awhile ago.  Looking more closely at the code, I am not sure I agree with the fact that there is any continuous assignment in here for the signal 'sig_read'.  I have highlighted the relevant code below.  According to the latest LRM clause 10.4, all cases of sig_read appear to be "triggered" assignments.  Specifically the one that he calls continuous is the instantiation of the dut, but in this case xbus_read is driven via an initial block and within and always procedural block.  These are both considered procedural assignments.  Am I missing something?

http://www.eda.org/svdb/view.php?id=3605

Thanks, -Tom


Below code show the problem in UBUS.
Variable sig_read is driven by both continous assignment in instance port and procedural assignment via virtual interface.
Such code is not currently officialy blocked by LRM but it is at least controversial.
Official example should not use such code pattern as good idea.

interface iface;
            logic clk;
            logic sig_read;
       endinterface

       module dut(input clk,output reg xbus_read);
            initial xbus_read<=1'bz;
            always @(posedge clk)begin
                xbus_read<=1'bz;
                $display("2: xbus_read<=1'bz");
            end
       endmodule

       class C;
            virtual iface vi;
            function new(virtual iface i);
                vi=i;
            endfunction
            function drive;
                vi.sig_read<=1;* //procedural drive of sig_read*
                $display("1: vi.sig_read<=1");
            endfunction
       endclass

       module top;
            iface iface_i();
            dut uut(iface_i.clk,iface_i.sig_read);* //dut instantation - continous drive of sig_read*
            C c =new(iface_i);
            initial iface_i.clk=0;
            always #5 iface_i.clk = ~ iface_i.clk;
            initial begin
                $display("START");
                 $monitor($time,">>>>", iface_i.sig_read);
                @(posedge iface_i.clk)
                c.drive();
                @(posedge iface_i.clk);
                #1;
                $display("END");
                assert(iface_i.sig_read)else $fatal("fatal error");
                $finish;
                end

       endmodule

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