RE: [sv-bc] use before declaration

Hi
This is because of compiler can only check for this error after reaching endmodule and that check will be based on the relative position of  "t.s" and "t" if they are in the same file or relative time of processing of "t.s" and "t" by the compiler if they are in different files. I don't think compiler developers will like to add this checking in code.
Thanks
Kausik


From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Radoslaw Nawrot
Sent: Thursday, December 05, 2013 6:34 PM
To: 'Bresticker, Shalom'; 'SV_BC List'
Subject: RE: [sv-bc] use before declaration

I think that reference to t  is a selection. Looks that (bacause of  identical syntax) tool's have problem with that. BTW "non-hierarchical " supervene only one time in LRM. Maybe this word should be changed or Glossary should be updated ,
Radek

________________________________
From: owner-sv-bc@eda.org<mailto:owner-sv-bc@eda.org> [mailto:owner-sv-bc@eda.org] On Behalf Of Bresticker, Shalom
Sent: Thursday, December 05, 2013 1:42 PM
To: SV_BC List
Subject: [sv-bc] use before declaration
Hi,

Why does the following not fail compilation?

module test;

wire w = t.s ;

struct { logic s; } t;

endmodule

6.21 says, "A variable declaration shall precede any simple reference (non-hierarchical) to that variable."

The reference to t is non-hierarchical, isn't it?

Thanks,
Shalom

Shalom Bresticker
Communications & Storage Infrastructure Group Silicon Engineering
Intel Jerusalem, Israel
+972  2 589 6582 (office)
+972 54 721 1033 (cell)
http://www.linkedin.com/in/shalombresticker


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