[sv-bc] RE: Query on cast operation

Hi Kausik,

Evaluation in the context of an assignment to a 4-bit vector is how that padding or truncation is achieved.

-- Brad

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Datta, Kausik
Sent: Tuesday, February 18, 2014 2:58 AM
To: Bresticker, Shalom; sv-bc@eda.org
Subject: [sv-bc] RE: Query on cast operation

Shalom,

LRM section 6.24.1 says

If the casting type is a constant expression with a positive integral value, the expression in parentheses shall
be padded or truncated to the size specified. It shall be an error if the size specified is zero or negative.

Doesn't this mean
4'(2'b10 + 1'b1 + 2'sb11) will be first evaluate
2'b10 + 1'b1 + 2'sb11 with size 2
And then will do the padding to size 4

Thanks
Kausik



From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com]
Sent: Tuesday, February 18, 2014 4:00 PM
To: Datta, Kausik; sv-bc@eda.org<mailto:sv-bc@eda.org>
Subject: RE: Query on cast operation

I tried 3 different major simulators (not the latest versions).
All 3 gave 6'b000110 for out6a.
Two gave the same for out6, one gave 6'b000010.

I think 6'b000110 is correct for both.

Shalom

From: owner-sv-bc@eda.org<mailto:owner-sv-bc@eda.org> [mailto:owner-sv-bc@eda.org] On Behalf Of Datta, Kausik
Sent: Tuesday, February 18, 2014 11:52
To: sv-bc@eda.org<mailto:sv-bc@eda.org>
Subject: [sv-bc] Query on cast operation

Hi,

For the below case, different tools interpret LRM differently.
Some evaluate the value of out6 and out6a 6'b000010 and some evaluate 6'b000110.

What should be the correct behavior?

My understanding of LRM is value of out6 should be 6'b000010 and that of out6a should be 6'b000110.

Thanks
Kausik


module cast39
  (input [1:0] in1,
   input signed [1:0] in2,
   output [5:0] out5, out5a, out6, out6a);

   typedef logic [3:0] bit4;

assign        out6  =    4'(2'b10 + 1'b1 + 2'sb11);
assign        out6a = bit4'(2'b10 + 1'b1 + 2'sb11);
endmodule

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