[sv-bc] RE: Query on cast operation

In section 6.24.1 Cast operator the LRM says:

<LRM>
If the casting type is a constant expression with a positive integral value, the expression in parentheses shall
be padded or truncated to the size specified. It shall be an error if the size specified is zero or negative.
</LRM>

A few paragraphs down the LRM says:

<LRM>
When changing the size, the cast shall return the value that a packed array type with a single [n-1:0]
dimension would hold after being assigned the expression, where n is the cast size. The signedness shall
pass through unchanged, i.e., the signedness of the result shall be the self-determined signedness of the
expression inside the cast. The array elements shall be of type bit if the expression inside the cast is 2-state,
otherwise they shall be of type logic.
</LRM>

Taken at face value, these two paragraphs are contradictory.  It you interpret the second paragraph as a refinement on the first, giving more details about how the padding or truncation is done, then it is clear the result of both expressions should be 6'b000110.

Adding to the confusion, in 10.8 Assignment-like contexts the LRM says:

<LRM>
No other contexts shall be considered assignment-like contexts. In particular, none of the following shall be
considered assignment-like contexts:
- A static cast
</LRM>

So a type or width cast is not an assignment like context, but type and width casts evaluate like an assignment.

There is no question this language causes confusion. I think we should revisit it and see if it can be made clearer.


From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Steven Sharp
Sent: Tuesday, February 18, 2014 12:35 PM
To: Datta, Kausik; Bresticker, Shalom; sv-bc@eda.org
Subject: [sv-bc] RE: Query on cast operation

Many of the operator descriptions include simplified descriptions of their bit-width behavior that are only correct when applied to simple operands, not to expressions.  For the general case, you have to look at the full rules for expression widths.  Padding is always done by setting the operand expression result width, which will then propagate down to any context-determined operands.  The rules work this way to prevent exactly the kind of unnecessary overflow that would otherwise occur in examples like yours.


From: owner-sv-bc@eda.org<mailto:owner-sv-bc@eda.org> [mailto:owner-sv-bc@eda.org] On Behalf Of Datta, Kausik
Sent: Tuesday, February 18, 2014 5:58 AM
To: Bresticker, Shalom; sv-bc@eda.org<mailto:sv-bc@eda.org>
Subject: [sv-bc] RE: Query on cast operation

Shalom,

LRM section 6.24.1 says

If the casting type is a constant expression with a positive integral value, the expression in parentheses shall
be padded or truncated to the size specified. It shall be an error if the size specified is zero or negative.

Doesn't this mean
4'(2'b10 + 1'b1 + 2'sb11) will be first evaluate
2'b10 + 1'b1 + 2'sb11 with size 2
And then will do the padding to size 4

Thanks
Kausik



From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com]
Sent: Tuesday, February 18, 2014 4:00 PM
To: Datta, Kausik; sv-bc@eda.org<mailto:sv-bc@eda.org>
Subject: RE: Query on cast operation

I tried 3 different major simulators (not the latest versions).
All 3 gave 6'b000110 for out6a.
Two gave the same for out6, one gave 6'b000010.

I think 6'b000110 is correct for both.

Shalom

From: owner-sv-bc@eda.org<mailto:owner-sv-bc@eda.org> [mailto:owner-sv-bc@eda.org] On Behalf Of Datta, Kausik
Sent: Tuesday, February 18, 2014 11:52
To: sv-bc@eda.org<mailto:sv-bc@eda.org>
Subject: [sv-bc] Query on cast operation

Hi,

For the below case, different tools interpret LRM differently.
Some evaluate the value of out6 and out6a 6'b000010 and some evaluate 6'b000110.

What should be the correct behavior?

My understanding of LRM is value of out6 should be 6'b000010 and that of out6a should be 6'b000110.

Thanks
Kausik


module cast39
  (input [1:0] in1,
   input signed [1:0] in2,
   output [5:0] out5, out5a, out6, out6a);

   typedef logic [3:0] bit4;

assign        out6  =    4'(2'b10 + 1'b1 + 2'sb11);
assign        out6a = bit4'(2'b10 + 1'b1 + 2'sb11);
endmodule

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