Re: [sv-bc] Should the LRM allow a frustrated bind statement?

Dave, I believe the forum thread is describing a very different concern.

Here's a minimalist example of the problem I'm discussing:

module instantiated_by_bind;
  ...
endmodule

module bind_target;
   ...
endmodule

module parameterized #(parameter num_targets = 1);
  if (num_targets > 0) begin
    bind_target [1:num_targets] target_instance ();
  end
endmodule

module top;
  parameterized #(.has_target(0)) empty_instance();
  bind bind_target instantiated_by_bind bound_instance();
endmodule

Assume, for now, that all modules except "top" are compiled
using -y, so they are not compiled unless used.

The problem is that, thanks to the parameterization of empty_instance(),
there is no target for the bind statement. For any values of has_target
greater than zero, everything is fine - each instance of "bind_target"
gets its own bound instance. But there's an obvious discontinuity
when has_target==0.

Inevitably, my desire for the simulator not to complain about this
is in conflict with the need to warn users about a completely wrong
or mis-spelt bind statement. But it is very inconvenient to be forced
to find some way to remove the bind statement completely if the
parameterization removes all its targets. In practical situations, the
bind statement is in a module that does not have easy access to
the parameter value.

Thanks

Jonathan Bromley


On 26 March 2014 15:18, Rich, Dave <Dave_Rich@mentor.com> wrote:

>  A very similar issue came up on one of the forums<https://verificationacademy.com/forums/systemverilog/i-have-share-moduleused-inside-many-other-modules-parameterizable-input/output-bus-width-how-do-i-write-sva-so-i-dont-have-bind-individual-instance>recently.  There is no way to connect the parameters of the target
> instances to the parameters bound instance. This may force you into the
> situation you encountered.
>
>
>
> Have you considered using a checker instead?
>
>
>
> Dave
>
>
>
>
>
> *From:* owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] *On Behalf Of *Jonathan
> Bromley
> *Sent:* Wednesday, March 26, 2014 4:23 AM
> *To:* sv-bc@eda.org
> *Subject:* [sv-bc] Should the LRM allow a frustrated bind statement?
>
>
>
> hello BC,
>
>
>
> We recently encountered a problem where we have a bind statement that
> specifies binding into a target module (not a named instance), but certain
> parameterizations of the design can cause there to be no elaborated
> instance of the target module. Tools complain about this, and that's
> probably correct per 1800-2012 because the preamble to 23.11 says
>
>
>
> "a bind construct that is used to specify one or more instantiations"
>
>
>
> I can't find any other part of the LRM that describes how to handle this
> situation, nor can I find any Mantis relating to it.
>
>
>
> In practice this corner case is extremely inconvenient, and it would be
> much preferable for tools to report only a warning in this case. Does SV-BC
> have an opinion on this? If there is no obvious reason for prohibiting such
> "frustrated" binds, I will raise a Mantis item about it.
>
>
>
> Thanks
>
>
>
> Jonathan Bromley
>
>
> --
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