RE: [sv-bc] Name of processes

Dave,

Don't you mean an if-generate plus a begin/end block?  I thought a begin/end block by itself was not legal as a module/generate item.

Synthesis tools may treat a named begin/end within the always block as the name of the always block:

   always @(posedge clk) begin: label
    end

Paul
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Rich, Dave
Sent: Wednesday, May 07, 2014 10:36 AM
To: Radosław Nawrot; 'SV_BC List'
Subject: RE: [sv-bc] Name of processes

Verilog already allows this by using a generate begin/end block. Why can that not be used?

begin: state_trigg

always @(posedge clk)
                 state<=next_state;
end

Attributes may also be used

(* state_trigg *) always @(posedge clk)
                 state<=next_state;

Both methods of assigning names allow retrieving those names from the VPI.

Dave


From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Radoslaw Nawrot
Sent: Wednesday, May 07, 2014 1:20 AM
To: 'SV_BC List'
Subject: [sv-bc] Name of processes

Hi,
It there any way to name process like always or initial ?
In my design,  body of many processes are changing while development. It would be nice to give them names which can be obtain in simulator (I'm not talking about comments) i.e in User interface or receive vpiName from vpiProcess
I know that I can name begin-end block but this is not actually the same thing.

simple example :

state_trigg: always @(posedge clk)
                 state<=next_state;

It would be nice to have such feature in standard

Best regards ,
Radek

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