[sv-bc] RE: unique and priority keywords for loops

Hi all,

A few have asked whether I'm interested in synthesis optimization or simulation assertions. I am most interested in synthesis optimization, but whatever solution must also provide for simulation assertions so not to fall into the pragma hole.

Noah

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Noah Kanovsky
Sent: Thursday, May 15, 2014 1:18 PM
To: 'SV_BC List'
Subject: [sv-bc] unique and priority keywords for loops

Hi,

Is there a way to accomplish unique / priority with a for or while loop? For example:

module test(
                input [3:0] sel_enc,
                input [3:0] in,
                output reg out
                );

always_comb begin
                out = 0;
                for(int i = 0; i < 5; i++) begin
                                priority if(sel_enc == i) begin
                                                out = in[i];
                                end
                end
end

endmodule

Most of my modules are parameterized, and these keywords don't help much when you can't write an explicit if else chain or case statement.
Noah

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