[sv-bc] RE: Binding to a parameterized module or interface

I can see now that I was looking at this from the wrong perspective.  What is in the LRM makes sense.  The issues that I am having then are truly tool issues.

Thanks,
-Brandon


From: Mark Hartoog [mailto:Mark.Hartoog@synopsys.com]
Sent: Tuesday, July 22, 2014 12:00 PM
To: Tipp, Brandon P; sv-bc@eda.org
Subject: RE: Binding to a parameterized module or interface

This is enhancement would raise some issues.

Any user defined types passed as type parameter overrides would have to be visible at the location of the bind.  This probably means they would have to be in a package or $unit.

This also raises questions about when binds are applied in the elaboration process.  This is not currently specified in the LRM.   Module parameter values can be defparamed.  I assume these binds would be applied after all defparams are applied at a level in the hierarchy.

The LRM in section 25.3 does say:

<LRM>
If the actual of an interface port connection is a hierarchical reference to an interface or a modport of a hierarchically referenced interface, the hierarchical reference shall refer to an interface instance and shall not resolve through an arrayed instance or a generate block.
</LRM>

This puts some restrictions on interface port connections, but it does not forbid an interface port to be connected to an instance created by a bind. As far as I know, many implementations of SV allow interface ports to be connected to instances created by binds.  Interface ports have to be hooked up before parameter values can be finalized at a given level of hierarchy. This is because the parameter values and types defined in the interface connected to the port can be accessed from the module it is connected to.  A bind created in this way could not be an interface instance that was connected to a interface port, at least not at the same level of the hierarchy.

As Greg has already pointed out, modules can also be "parameterized" by the interfaces connected to their interface ports, so this is not a completely specification of a parameterized module.

From: owner-sv-bc@eda.org<mailto:owner-sv-bc@eda.org> [mailto:owner-sv-bc@eda.org] On Behalf Of Tipp, Brandon P
Sent: Tuesday, July 22, 2014 11:15 AM
To: sv-bc@eda.org<mailto:sv-bc@eda.org>
Subject: [sv-bc] Binding to a parameterized module or interface

This is related to Daniel's e-mail here http://www.eda.org/sv-bc/hm/11570.html.  I am trying to bind a parameterized module to a parameterized module, however it confuses the simulator and it won't build properly.  The spec should allow me to bind to a specific specialization of a paramterized module, but the BNF for bind doesn't allow that.  Instead of this:

bind_directive ::=
    bind bind_target_scope [: bind_target_instance_list] bind_instantiation ;
  | bind bind_target_instance bind_instantiation ;
bind_target_scope ::=
    module_identifier
  | interface_identifier

It should be this:

bind_directive ::=
    bind bind_target_scope [ parameter_value_assignment ] [: bind_target_instance_list] bind_instantiation ;
  | bind bind_target_instance bind_instantiation ;
bind_target_scope ::=
    module_identifier
  | interface_identifier

Also, if it is legal to bind to all specializations of a parameterized module, the spec needs to clarify that binding to a parameterized module/interface without specifying parameter port assignments should apply to all specializations of the module/interface, not only the default specialization.

-Brandon

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