I'm not sure
if Dave's interpretation comes from explicit LRM rule.
LRM for says only that UAC: elements shall be interpreted as
: "An item whose self-determined type is
assignmentcompatible with the element type of the target
array shall represent a single element" but does not say how
assignment should be performed. IMHO each element assignment
should be done according to general SV rules so A[0] would
be 4'b1111 according to Dave interpretation special
assignment similar to vector concatenation should be done.
Maybe I'm missing something but imho this case is in
grey/undefined area of LRM. I think that rule cited above
was added to define cases where element by element
assignment are possible vs cases other cases possible in
UAC, not to define assignment rules
DANiel
W dniu 7/23/2014 4:25 PM, Rich, Dave
pisze:
The
operands in an unpacked array concatenation are
self-determined, just like Verilog integral
concatenation. So 1’b1 should be the result. Assignment
patterns are context determined. This is one of the key
distinctions between the two forms.
Dave
In SV 1800-2009 concatenations could be
used as source expressions for unpacked arrays (section
10.10). I have a query regarding usage of `1 in unpacked
array concatenation. If the RTL has something like below
logic [3:0] A [0:0];
initial
begin
A = {‘1};
end
Does this mean that the value of A[0]
after assignment will be “1111” or will it be “0001”?
Thanks & Regards
Rohit Goel
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