[sv-bc] empty 'design' ?

From: Bresticker, Shalom <shalom.bresticker@intel.com>
Date: Mon Oct 13 2014 - 05:22:59 PDT
The syntax of the design statement in configurations is:

design_statement ::= design { [ library_identifier . ] cell_identifier } ;

Since curly brackets are used, a syntactically legal statement would be 'design ;'.

Was their ever any intent to allow this?

Or are the curly brackets only intended to allow multiple specifications in a design statement?

Thanks,
Shalom

Shalom Bresticker
Communications & Storage Infrastructure Group Design Automation
Intel Jerusalem, Israel
+972  2 589 6582 (office)
+972 54 721 1033 (cell)
http://www.linkedin.com/in/shalombresticker
The devil is in the details.

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Received on Mon Oct 13 05:23:14 2014

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