[sv-bc] RE: Scoping Next 1800 Effort - Due EO February

This conflicts with the ongoing UVM WG meeting time Matt.  I won't be able to make either meeting.  I will hit up the UVM committee tomorrow to ask for input.  -Tom

-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Mark Hartoog
Sent: Tuesday, February 17, 2015 11:49 AM
To: Maidment, Matthew R; sv-bc@eda.org; sv-ec@eda.org
Subject: [sv-ec] RE: Scoping Next 1800 Effort - Due EO February

Is there still going to be a conference call tomorrow, Wednesday, February 18th?

-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Maidment, Matthew R
Sent: Wednesday, February 04, 2015 7:05 AM
To: sv-bc@eda.org; sv-ec@eda.org
Subject: [sv-ec] Scoping Next 1800 Effort - Due EO February

Hi SV-BC & SV-EC members.

The 1800 WG is exploring restarting SystemVerilog standards work.  To that end they've asked for input from the technical subcommittees about the scope and nature of such an effort.

There will be a meeting March 6 in San Jose to cover input on the matter from the technical sub-committees.

Given that the membership of the two sub-committees overlaps quite significantly I suggest that SV-BC and SV-EC work together to assemble input.  Here's the process I suggest over the course of February:

1.      Identify Mantis items or new issues over the next two weeks and summarize your input to the SV-BC and SV-EC reflectors.
2.      Hold conference calls Wednesday, February 18 and Wednesday, February 25 from 9-11am PST to assemble, refine, prioritize and summarize the input from the committees

I will send out a detailed meeting agenda and dial-in information ahead of each call.

Thanks,

Matt



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