[sv-bc] RE: Scoping Next 1800 Effort - Due EO February

I've received feedback in support of:

0002735: Chaining of method calls. http://www.eda.org/svdb/view.php?id=2735
0002996: Method overloading. http://www.eda.org/svdb/view.php?id=2996
0003054: System functions in constraints. http://www.eda.org/svdb/view.php?id=3054

I've also had the following suggested (which I haven't found a Mantis for):

- Add ability to extend interfaces (e.g., define base AXI interface and have ACE interface be an extension of that so can parallel class inheritance hierarchy).

From, Daniel.

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Maidment, Matthew R
Sent: 04 February 2015 15:05
To: sv-bc@eda.org; sv-ec@eda.org
Subject: [sv-bc] Scoping Next 1800 Effort - Due EO February

Hi SV-BC & SV-EC members.

The 1800 WG is exploring restarting SystemVerilog standards work.  To that end they've asked for input from the technical subcommittees about the scope and nature of such an effort.

There will be a meeting March 6 in San Jose to cover input on the matter from the technical sub-committees.

Given that the membership of the two sub-committees overlaps quite significantly I suggest that SV-BC and SV-EC work together to assemble input.  Here's the process I suggest over the course of February:

1.      Identify Mantis items or new issues over the next two weeks and summarize your input to the SV-BC and SV-EC reflectors.
2.      Hold conference calls Wednesday, February 18 and Wednesday, February 25 from 9-11am PST to assemble, refine, prioritize and summarize the input from the committees

I will send out a detailed meeting agenda and dial-in information ahead of each call.

Thanks,

Matt



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