[sv-bc] RE: Connecting generated interface instances

I believe that the reason is to prevent circularity.  It is the same reason that you are not allowed to have a defparam inside a generate block that affects a parameter outside the generate block.  It could affect a parameter that controls the generate block, possibly changing it so that the defparam should not have been generated after all.

A defparam can "push" a parameter value from inside the generate block to a parameter outside the generate block.  Connecting an actual of an interface port to a hierarchical reference to an interface inside a generate block could "pull" a parameter value from inside the generate block to a parameter outside the generate block.  After you have the reference to the interface instance outside the generate block, you can extract a parameter value out of the interface instance by going through an interface-based typedef.

Suppose you have a parameter inside a generate block.  You instantiate an interface inside that generate block, parameterized with the given parameter.  The interface declares a typedef that is a vector whose width is set by the parameter.  Then you connect that interface to an interface port outside the generate, perhaps a port of the module containing the generate.  That module then uses an interface-based typedef to access that type.  Then it uses $bits on that type to set a parameter, which now matches the parameter inside the generate block.  Now you can use that parameter to control the generate block, creating a circular situation.


From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Bresticker, Shalom
Sent: Sunday, February 22, 2015 2:53 AM
To: sv-bc@eda.org
Subject: [sv-bc] RE: Connecting generated interface instances

The LRM says in 25.3,

"If the actual of an interface port connection is a hierarchical reference to an interface ..., the hierarchical reference shall refer to an interface instance and shall not resolve through ... a generate block."

What is the reason for this restriction ?

Example:

///////////////////// Beginning of code ///////////////////////

interface if1 ();
endinterface

module module1 (if1 if1_inst);
endmodule

module test();
      generate
            for (genvar i=0; i<2; i++) begin : if_gen
                  if1 if1_inst();
            end
      endgenerate

      module1 module1_inst
            (
            .if1_inst(if_gen[0].if1_inst)
            );

endmodule

//////////////////////// End of code /////////////////////////

I saw 2 major compilers reject this code due to the above restriction.

Thanks,
Shalom

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