Re: [sv-bc] Re: What is the type of a slice?

The LRM doesn't say.

The only related statement is in 11.4.12:  "One or more bits of a 
concatenation can be selected as if the concatenation were a packed 
array with the range [n-1:0]" which applies only to concats and then 
only in the context of a select.  The "as if" part of the statement 
should be a good indicator that there is no definition -- the select 
behaves "as if" the concat result is typed in that manner but it makes 
no claim about the *actual* type of the concat result.

Traditionally all operations in Verilog have only cared about widths 
since intermediate results weren't valid in indexing operations, there 
aren't "unconstrained arrays" in the VHDL sense, and there was no way to 
have type inspection.  The type operator exposes type detail in various 
ways that impacts that.

It would likely be very difficult to get agreement on any definition in 
the LRM.

I'd probably be more inclined to make it a user problem.  If, in your 
example, the user "expects" the result "1" then they should (be able to) 
build the comparison as:
      $size(type(v[3:2])) == $size(type(v[1:0]))
or build a "normalized type" as:
      typedef bit T [$size(type(v[3:2])) -1 : 0]
or similar.

There is a fair amount of pain in VHDL in terms of managing the type 
rules related to clear definitions for all sub-expression types and I'd 
prefer to not go that way in SV.

Gord.


On 9/16/15 2:36 AM, Brad Pierce wrote:
>
> Following up to http://www.eda.org/sv-bc/hm/11749.html 
> <http://www.eda.org/sv-bc/hm/11749.html> , does the following display 
> 1 or 0?
>
> *module*test(*output* out);
>
> *bit* v[3:0];
>
> *if* (*type*(v[3:2]) == *type*(v[1:0]))
>
> *assign* out = 1'b1;
>
> *else*
>
> *assign* out = 1'b0;
>
> *initial begin*
>
>   #1 $display(out);
>
> *end*
>
> *endmodule*
>
> **
>
> -- Brad
>
>
> -- 
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Gordon Vreugdenhil                                503-685-0808
Verification Technologies, Mentor Graphics        gordonv@model.com


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