Subject: [sv-bc] Section 19 updates - alias removed - comments please!
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Thu Dec 11 2003 - 11:22:54 PST
Hi, All -
I shed a few tears and removed all of the "alias" references, except one
(see section 19.4). Section 19.4 is the second place where the
documentation refers to an instance name in the module header, which is
clearly wrong. I tried to explain it in non-alias terms, but added an
"alias within parentheses to help the explanation. I am open to corrections.
Please review and respond ASAP. If we want to add these corrections before
closing debate, it has to be done by tomorrow.
Regards - Cliff
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training
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