Subject: RE: [sv-bc] Section 19 updates - alias removed - comments please!
From: Warmke, Doug (doug_warmke@mentorg.com)
Date: Tue Dec 16 2003 - 09:25:00 PST
Hi Everyone,
We've reviewed Cliff's proposed changes.
One of us is ambivalent at best, another of us thinks they're OK,
and I like them in general. So if there is a vote needed in order
to get these changes included, we would vote "yes go for it".
One interesting question came up in the debate:
As most people on this reflector know, Verilog simulators silently
ignore port directionality information. Nets are created, connected,
and then driven whereever they need to go, regardless of "input",
"output", and "inout" port directionality.
We were wondering if the same loose rules are intended to be applied
to modport directionality information? We hope not, since such
information can be useful self-documenting design code.
But we thought we'd ask, just to be safe.
Regards,
Doug Warmke
> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On
> Behalf Of Clifford E. Cummings
> Sent: Thursday, December 11, 2003 11:23 AM
> To: sv-bc@eda.org
> Subject: [sv-bc] Section 19 updates - alias removed - comments please!
> Importance: High
>
>
> Hi, All -
>
> I shed a few tears and removed all of the "alias" references,
> except one
> (see section 19.4). Section 19.4 is the second place where the
> documentation refers to an instance name in the module
> header, which is
> clearly wrong. I tried to explain it in non-alias terms, but added an
> "alias within parentheses to help the explanation. I am open
> to corrections.
>
> Please review and respond ASAP. If we want to add these
> corrections before
> closing debate, it has to be done by tomorrow.
>
> Regards - Cliff
>
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com
> Expert Verilog, SystemVerilog, Synthesis and Verification Training
>
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